Low Phase Noise Oscillator Design. A Design Methodology for Improving Performance: Theoretical Analysis, CAD Simulations, and Prototype Building
Mansour, Makram Monzer
This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/80895
Description
Title
Low Phase Noise Oscillator Design. A Design Methodology for Improving Performance: Theoretical Analysis, CAD Simulations, and Prototype Building
Author(s)
Mansour, Makram Monzer
Issue Date
2004
Doctoral Committee Chair(s)
Mehrotra, Amit
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
This research encompasses theoretical as well as practical aspects in the design of low phase noise LC-tank CMOS RF oscillators. Novel analytical techniques for estimating the periodic steady-state solution, perturbation-projection vector, and phase noise/timing jitter for oscillators are presented. These techniques enable a quantitative estimate of the oscillator phase noise/timing jitter performance from its constituent circuit characteristics with high accuracy. Further, the engineering techniques presented provide insight and quantitative understanding of current-day deep-submicron CMOS LC-tank oscillator design, and serve as a starting point in a design strategy that includes a complete phase noise/timing jitter optimization. The analytical results presented in this work have been verified by extensive CAD simulations using Berkeley Design Automation's advanced RF circuit simulator. A new quadrature phase oscillator architecture which has lower phase noise performance than the leading current day architectures is presented, and its performance is verified with simulations and chip measurements. Fourteen oscillators consisting of 7 voltage-controlled oscillators, 3 oscillators, and 4 quadrature-phase VCOs, as well as a low-noise amplifier, and individual device characterization and cancellation structures were fabricated using Fujitsu Laboratories of America 0.11-mum, 1.2-V CMOS silicon express technology. The chips were successfully tested at the Berkeley Wireless Research Center at the University of California at Berkeley and the performance of five of these oscillators is also presented in this work.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
