Algorithms and Architectures for Joint Equalization and Decoding
Lee, Seok-Jun
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https://hdl.handle.net/2142/80893
Description
Title
Algorithms and Architectures for Joint Equalization and Decoding
Author(s)
Lee, Seok-Jun
Issue Date
2004
Doctoral Committee Chair(s)
Shanbhag, Naresh R.
Singer, Andrew C.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Various linear turbo equalizer VLSI architectures are explored. Energy-efficient architectures that eliminate redundant operations and employing early termination achieve power savings up to 60%. To improve the throughput, a concurrent processing VLSI architecture is proposed, where SISO equalizers and decoders are running concurrently, thereby increasing throughput by up to 75%. To improve the BER further, a class of switching linear turbo equalizers is also shown along with several feasible switching schemes.
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