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https://hdl.handle.net/2142/80871
Description
Title
Noise -Tolerant Digital System Design
Author(s)
Balamurugan, Ganesh
Issue Date
2004
Doctoral Committee Chair(s)
Naresh Shanbhag
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
In addition to ISI, jitter also limits performance in high-speed I/O links. A discrete-time model that comprehends both transmit and receive jitter is presented. Typical I/O channels are shown to amplify high-frequency transmit jitter limiting the performance of equalization and multilevel signaling schemes. Design techniques to mitigate the effect of jitter are also presented.
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