SOI Circuit Design Styles and High-Level Circuit Modeling Techniques
Kanj, Rouwaida
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https://hdl.handle.net/2142/80867
Description
Title
SOI Circuit Design Styles and High-Level Circuit Modeling Techniques
Author(s)
Kanj, Rouwaida
Issue Date
2004
Doctoral Committee Chair(s)
Rosenbaum, Elyse
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Cell-based noise analysis tools. In advanced SOI technologies, the input noise may propagate, with little attenuation, through several or many gates. Therefore, accurately modeling noise propagation (from a cell's inputs to its outputs) is of significant importance for cell-based noise analysis tools. We propose and implement two new macromodeling techniques for purposes of building a noise-rule library. Our models capture the cell's output response due to noise at its input. Thus, one may accurately predict the propagated noise, perform failure/sensitivity (stability) analysis, or even hierarchically build the noise abstracts by invoking those high-level macromodels.
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