Characterization, Design, and Modeling of on -Chip Electrostatic Discharge Protection Devices
Li, Junjun
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https://hdl.handle.net/2142/80861
Description
Title
Characterization, Design, and Modeling of on -Chip Electrostatic Discharge Protection Devices
Author(s)
Li, Junjun
Issue Date
2004
Doctoral Committee Chair(s)
Rosenbaum, Elyse
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
In this dissertation, extensive results are presented on characterization, design, and modeling of on-chip ESD protection devices. Specifically, simulator-independent circuit-level compact models for ESD protection NMOSFETs and diodes are developed using the Verilog-A language. Model confirmations are obtained through experimental data of a 0.6-mum, and a 0.13-mum CMOS technology. Small-signal and large-signal models are provided to ensure accurate ac and transient simulation. Improved avalanche multiplication factor equations are used to avoid convergence problems. Key modeling parameters are analyzed and important elements identified for accurate capture of the trigger voltage. Various trigger mechanisms are then studied to further understand the NMOS transient snapback behavior. Compact models of the on-resistance are proposed to incorporate the self-heating effect. Investigations on the turn-on behaviors of ESD protection MOSFETs and diodes reveal clear voltage overshooting with the help of an improved VFTLP (Very Fast Transmission Line Pulsing) system. Next, the ESD robustness of a 0.13-mum CMOS technology is carefully evaluated with design considerations given. Last, design techniques of RC-triggered, MOSFET based power clamps are discussed. A compact, timed-shutoff power clamp is proposed for area reduction and performance improvement.
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