Power Distribution Network Analysis and Optimization in Digital VLSI Circuits
Bai, Geng
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https://hdl.handle.net/2142/80853
Description
Title
Power Distribution Network Analysis and Optimization in Digital VLSI Circuits
Author(s)
Bai, Geng
Issue Date
2004
Doctoral Committee Chair(s)
Hajj, Ibrahim N.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
We propose a novel approach to the analysis and design of reliable power distribution networks for digital VLSI circuits. The optimized power and ground buses should meet or outperform the noise level specifications while achieving minimum die size. The flow consists of two main steps: analysis and optimization. During the analysis phase, the power and ground buses are broken down into multilevel hierarchical structures. Different algorithms are employed for the analysis at different hierarchies. In all the analyses, input-independent algorithms are used to reduce simulation time and obtain an accurate noise upper bound. Additional techniques (namely, sensitivity analysis, constraint graph optimization, and reduced order modeling techniques) are also employed to improve the accuracy with little overhead in terms of the simulation time. An algorithm is developed to determine the conditions that will cause maximum delay along target critical paths with power/ground bus voltage variation effects. Finally, new techniques for decoupling capacitance placement and power grid area optimization are presented.
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