Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology
Jung, Seong-Ook
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https://hdl.handle.net/2142/80764
Description
Title
Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology
Author(s)
Jung, Seong-Ook
Issue Date
2002
Doctoral Committee Chair(s)
Kang, Sung-Mo (Steve)
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Domino logic is known to consume more dynamic power than static logic. Low-voltage swing clock domino logic family is developed for substantial dynamic power saving. Delay-constrained power optimization algorithm allocates low supply voltage to logic gates such that dynamic power is minimized with timing constraint. Timing accuracy is ensured by accounting for timing variations due to gate-to-source voltage and input arrival time difference.
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