High-Speed, Low-Spurious CMOS Analog -to -Digital Converter
Choe, Myung-Jun
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https://hdl.handle.net/2142/80747
Description
Title
High-Speed, Low-Spurious CMOS Analog -to -Digital Converter
Author(s)
Choe, Myung-Jun
Issue Date
2001
Doctoral Committee Chair(s)
Song, Bang-Sup
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Pipelining not only provides a speed advantage, but also enables the application of background offset trimming to folding ADCs. Background offset trimming with a delta-sigma modulator is applied to compensate the random input offset of folding amplifiers. A subranging front-end is used in conjunction with the pipelined folding ADC to make the calibration feasible. The second prototype chip was measured to exhibit 40 Msamples/s conversion rate with 13-bit resolution, consuming 800 mW at 5 V.
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