Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques
Yoo, Seung-Moon
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https://hdl.handle.net/2142/80745
Description
Title
Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques
Author(s)
Yoo, Seung-Moon
Issue Date
2001
Doctoral Committee Chair(s)
Kang, Sung-Mo (Steve)
Torrellas, Josep
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
To tackle problems such as tremendously increased leakage current and power consumption due to the scaled threshold voltage of the transistor and increased number of gates in future VLSI chips, sub-1-V circuit techniques to suppress leakage current while meeting performance requirement are developed. High efficient charge recycling logic using charge sharing in the precharge cycle with no pre-evaluation problems and using ac power clocks with bootstrapped NMOS transistors are designed to reduce active power consumption further.
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