University of Illinois Urbana-Champaign

Tunneling Real-Space Transfer Transistor Circuit Model

Hendren, Lucas

Content Files
ECE499-Sp2015-hendren.pdf

Permalink

https://hdl.handle.net/2142/79039

Description

Title
Tunneling Real-Space Transfer Transistor Circuit Model
Author(s)
Hendren, Lucas
Contributor(s)
Leburton, Jean-Pierre
Issue Date
2015-05
Keyword(s)
  • Tunneling Real-Space Transfer Transistor Circuit Model
  • Tunneling
  • Circuit model
Date of Ingest
2015-08-13T16:10:00Z
Abstract
This research involves the investigation of tunneling real-space transfer transistor with abrupt negative differential resistance (NDR), on the nano-scale. Our Tunneling Real-Space Transfer Transistor is composed of a gallium arsenide, indium gallium arsenide, and gallium arsenide layer. Our Tunneling Real-Space Transfer Transistor works by the current leaking to the gate via wave function hybridization of the indium gallium arsenide layer with the quantized states of the gallium arsenide top layer based on the parameters of the gate-drain bias. The purpose this research is to show that this device can be scaled down to nano-scale feature size to reduce the intrinsic capacitance and the resistive effect to see if the device can operate at high speed. The main concern is to maintain a large gate tunneling current leaking from the drain to gate leading to an abrupt negative differential resistance. To solve this problem, the device equation was first derived for the macro-scale, and then the models of the equations were compared to the test results of the macro-scale. After that we used these values to derive the circuit model and load line.
Type of Resource
text
Genre of Resource
Other
Language
en
Permalink
http://hdl.handle.net/2142/79039

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