Hierarchical and scalable bus architecture generation on FPGAs with high-level synthesis

Chen, Ying

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https://hdl.handle.net/2142/78686 Copy

Description

Title

Hierarchical and scalable bus architecture generation on FPGAs with high-level synthesis

Author(s)

Chen, Ying

Issue Date

2015-04-30

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• FCUDA
• Advanced eXtensible Interface (AXI)
• BUS
• High-Level Synthesis
• Compute Unified Device Architecture (CUDA)

Abstract

This thesis presents and evaluates a bus-based system for FCUDA, a translation tool enabling CUDA code to be run on FPGAs. With the goal of constructing a solid light-weight back-end with optimized performance, we choose AXI4 as the communication protocol and plug in all necessary components on a hierarchical bus system. Then, FCUDA cores are added in the back-end and the comprehensive system is automated into a single tool chain. Several optimizations are added in this automated FCUDA bus system for the delivery of better performance. For example, FCUDA cores are tiled into clusters based on configuration inputs, and clock domains are separated to reduce long wires. For the experiments, this work adjusts the existing resources and period models and enhances the system latency model by incorporating off-chip memory communication latency. The system is proved to be light-weight based on post-routing resource reports. Design space exploration among multilevel granularity parallelisms is performed to get the system's best performance, with which a comparison with GPU is made. Our system can achieve at most 2.08 performance improvement when compared with the execution latency on GPU.

Graduation Semester

2015-5

Type of Resource

text

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http://hdl.handle.net/2142/78686

Copyright and License Information

Copyright 2015 Ying Chen

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