Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA)
Li, Shuo
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LI-THESIS-2015.pdf
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https://hdl.handle.net/2142/78598
Description
Title
Tutorial on designing and simulating a truncation spurs-free direct digital synthesizer (DDS) on a field-programmable gate array (FPGA)
Author(s)
Li, Shuo
Issue Date
2015-04-07
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Date of Ingest
2015-07-22T22:33:11Z
Keyword(s)
direct digital synthesizer (DDS)
Field-Programmable Gate Array (FPGA)
digital design
Abstract
Direct digital synthesis is a technique for using digital data processing blocks as a means to generate a frequency and phase tunable output signal referenced to a fixed-frequency precision clock source. Many telecommunication applications require such a high-speed switching, fine- tuning and superior quality signal source for their components. This thesis will introduce the direct digital synthesizer (DDS) and investigate the signal integrity issues associated with the DDS design.
In order to minimize the size of the lookup table to save hardware and lower the power consumption, we normally truncate the phase word output from the phase accumulator in the standard approach of designing DDS. However, this process will generate spurious frequencies (spurs), which degrade the quality of the output signals. It is considered one of the main signal integrity issues in the DDS design.
Previous research introduces a novel spurs-free truncation method for compressing the lookup table to avoid using phase truncation without significant hardware change. This thesis aims to implement this DDS with novel truncation spurs-free structure and test it in a practical environment. It does so by providing a tutorial on designing, implementing and simulating the DDS on an Altera DE2-115 FPGA using Altera Quartus II FPGA design software and ModelSim Simulator. The Verilog hardware description language is used as the development language.
This thesis will describe entire designs of both DDS with traditional structure and DDS with novel truncation spurs-free structure. By comparing the outputs, it also examines the corresponding simulation results and verifies the improvement of the signal quality.
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LI-THESIS-2015.pdf
