University of Illinois Urbana-Champaign

Fault tolerance core: a framework for application-aware reliability

Sidea, Valentin

Content Files
SIDEA-THESIS-2015.pdf

Permalink

https://hdl.handle.net/2142/78280

Description

Title
Fault tolerance core: a framework for application-aware reliability
Author(s)
Sidea, Valentin
Issue Date
2015-04-28
Committee Member(s)
Kalbarczyk, Zbigniew T
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Date of Ingest
2015-07-22T22:15:19Z
Keyword(s)
  • Fault Tolerance
  • Reliability
Abstract
As processor manufacturers keep pushing the limits of the transistor, the reliability of computer systems has become an increasing concern. Various fault tolerance techniques have been developed in an effort to provide reliable computing in the presence of faults. These approaches suffer from either a high resource cost or high performance overhead. This thesis presents a design for a Fault Tolerance Core (FTC) that uses configurable application-aware hardware modules for improving reliability. Application-aware fault tolerance is achieved by detecting perturbations in application execution through the monitoring of processor pipeline signals. This approach leverages hardware resources more efficiently than replication. The FTC achieves low overhead by placing fault tolerance hardware separately from the processing core, minimizing the processor data collection hardware, and by performing fault detection in the background. This thesis presents work that has been completed towards the achievement of a FTC. This work includes a hardware assisted incremental checkpoint, an application hang detector and a preliminary FTC framework for integrating these into a Leon3 microprocessor. All modules have been implemented and tested on a Leon3 synthesized atop a Stratix III FPGA running a Linux environment. A hardware fault injector capable of modifying 9 distinct processor pipeline signals has been implemented for performing validation experiments on the modules.
Graduation Semester
2015-5
Type of Resource
text
Permalink
http://hdl.handle.net/2142/78280
Copyright and License Information
Copyright 2015 Valentin Sidea

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