Logic upset induced by substrate current during power-on ESD
Xiu, Yang
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https://hdl.handle.net/2142/73003
Description
Title
Logic upset induced by substrate current during power-on ESD
Author(s)
Xiu, Yang
Issue Date
2015-01-21
Director of Research (if dissertation) or Advisor (if thesis)
Rosenbaum, Elyse
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
power-on electrostatic discharge (ESD)
soft failure
substrate current
system-level electrostatic discharge (ESD)
Abstract
In this thesis, we will describe an experimental study of one possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry.
This type of upset often involves contention between the transistor and the parasitic structure. Therefore, the likelihood for logic upsets to occur is sensitive to transistor sizing, as well as the collection efficiency of the parasitic structure. The collection efficiency is affected by various factors, including spacing and collector size.
The occurrence of logic upsets is dependent on the ESD pulse injected. They are observed during transmission line pulses of various widths, where the upset pattern changes according to the pulse width. Upsets are also observed during system-level ESD tests, such as the ISO 10605 stress.
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