Improved Algorithms for Cell Placement and Their Parallel Implementations
Kim, Sungho
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https://hdl.handle.net/2142/72013
Description
Title
Improved Algorithms for Cell Placement and Their Parallel Implementations
Author(s)
Kim, Sungho
Issue Date
1993
Doctoral Committee Chair(s)
Banerjee, Prithviraj
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Abstract
As the size of modern VLSI circuits increases, new problems are emerging in the VLSI CAD area. The circuit is becoming more difficult to test, the circuit performances are greatly influenced by the physical layout, and the computation times taken by a lay-out CAD tool are becoming prohibitively large. No conventional physical design CAD tools, however, have been able to overcome these new emerging problems altogether. In this thesis, we present a novel VLSI placement algorithm (APT: An area-performance-testability driven placement algorithm) to produce a placement that not only meets the area requirement of the circuit but also meets the timing and the testability requirements as well. In APT, the multiple objectives are met by (1) assigning an upper timing bound to each net, (2) allowing cell resizing using the multiple templates provided by the cell library and (3) using the notion of partial scan technique. In addition, we have implemented a parallel placement algorithm (ProperPLACE: An asynchronous portable parallel algorithm for placement) and have shown that the computation time can significantly be reduced by using a parallel processor or a network of workstations, without degrading its solution quality. ProperPLACE has three significant contributions: (1) It is portable across MIMD machines by building it around the ProperCAD environment. (2) It is built around an existing sequential placement (TimberwolfSC version 6.0) using a well-defined interface. (3) It is an asynchronous parallel simulated annealing algorithm with an error control mechanism. The experimental results on the ISCAS benchmark circuits show that the layouts produced by APT are better than the results of TimberWolf (an existing well-known cell placement program) in terms of performance and fault coverage. Results on the circuits in the ISCAS benchmarks and in Physical Design Workshop 91 show that ProperPLACE successfully produces placement solutions with the quality equivalent to that of TimberWolfSC version 6.0, but at a much greater speed. The ProperPLACE program runs on a variety of parallel machines supported by ProperCAD such as the Encore Multimax, the Intel i860 hypercube, the Sequent Symmetry, a network of Sun Sparc workstations without any change to its code.
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