Parallel Circuit Simulation Techniques for a Hierarchical Machine
Hung, Gih-Guang
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Permalink
https://hdl.handle.net/2142/72012
Description
Title
Parallel Circuit Simulation Techniques for a Hierarchical Machine
Author(s)
Hung, Gih-Guang
Issue Date
1993
Doctoral Committee Chair(s)
Gallivan, Kyle A.
Saleh, Resve A.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Abstract
Circuit simulation remains an indispensable tool in the CAD community and is used widely to verify circuit functionality and to generate detailed timing information. As circuit designers push the limits on chip density and complexity, more powerful parallel processing resources and more efficient techniques are needed to speed up the simulation process. This dissertation addresses some general issues in parallel circuit simulation and investigates a variety of classical algorithms on the Cedar multiprocessor. Unfortunately, the range of behavior observed for these algorithms applied to various types of circuits is considerable. In an attempt to combine the advantages of several well-established algorithms, a hierarchical framework called CedarSim is proposed. This framework uses a hierarchical relaxation approach and allows different combinations of algorithms to be used at different levels. The objective is to allow each subcircuit to be solved using the most appropriate technique. This flexibility makes it possible to switch between standard and hierarchical algorithms to adapt to varying conditions. The proper functioning of this framework also hinges on appropriate circuit partitioning and effective algorithm selection, which are major research topics by themselves. This dissertation shows that, given proper mechanisms for these two tasks, CedarSim can deliver reasonable performance. This framework can also adapt to poor partitioning by using hierarchical relaxation and aggressive latency exploitation in several algorithms. Performance evaluation tools and techniques are used extensively to understand the behavior of the algorithms and the architecture and to study the interactions between various performance issues. Observations on the strengths and weaknesses of machines such as Cedar are also made. The knowledge acquired in this work also serves as a guideline for a more ambitious goal of developing a portable parallel circuit simulator.
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