Periodic Application of Concurrent Error Detection in Processor Array Architectures
Chen, Paul Peichuan
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https://hdl.handle.net/2142/71998
Description
Title
Periodic Application of Concurrent Error Detection in Processor Array Architectures
Author(s)
Chen, Paul Peichuan
Issue Date
1993
Doctoral Committee Chair(s)
Fuchs, W. Kent
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Abstract
Processor arrays can provide an attractive architecture for some applications. Featuring modularity, regular interconnection and high parallelism, such arrays are well-suited for VLSI/WSI implementations, and applications with high computational requirements, such as real-time signal processing.
Preserving the integrity of results can be of paramount importance for certain applications. In these cases, fault tolerance should be used to ensure reliable delivery of a system's service. One aspect of fault tolerance is the detection of errors caused by faults. Concurrent error detection (CED) techniques offer the advantage that transient and intermittent faults may be detected with greater probability than with off-line diagnostic tests. Applying time-redundant CED techniques can reduce hardware redundancy costs. However, most time-redundant CED techniques degrade a system's performance.
Periodic Application of Concurrent Error Detection (PACED) is a technique introduced in this thesis to reduce the performance costs incurred through the use of time-redundant CED in processor array architectures. To check computations periodically instead of continuously, PACED varies the application of such CED techniques to a processor array in both time and space. The purpose of PACED is to provide probabilistic detection of transient, intermittent, and permanent failures in processor arrays while reducing the overhead of performing detection.
Since CED is not performed continuously when PACED is used, undetected errors may occur prior to an error indication. Therefore, upon error detection, not only the current outputs of the array but both recent and subsequent outputs may also be erroneous. This thesis investigates the confidence to place on system outputs when PACED is applied, deriving formulae to predict the amount of output to suspect as possibly erroneous for single processors, linear unidirectional and two-dimensional mesh-connected processor arrays. The error coverage afforded by PACED in these architectures is also studied. Finally, the performance impact of using PACED in each array type is studied using both an array simulation model that gives estimates of application completion times with low computational cost and results of experiments using an Intel iPSC/2 hypercube to simulate a 16-node unidirectional linear array and a 4 x 4 two-dimensional mesh array.
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