Architectural Level Test Generation and Fault Simulation
Lee, Jaushin
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https://hdl.handle.net/2142/71982
Description
Title
Architectural Level Test Generation and Fault Simulation
Author(s)
Lee, Jaushin
Issue Date
1992
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Abstract
In this thesis, a high level branch-and-bound based ATPG approach will be first presented. This method is a reasonable extension of the gate level ATPG approaches. Although various effective techniques have been applied, this method has sluggish performance for circuits with complicated data path or control. The second approach, based on a nonlinear equation solving, is proposed to overcome the difficulties. The test generation process is separated into two phases. An instruction sequence assembling methodology is developed in the first phase to search for a valid instruction sequence for the injected test vector of the module under test. In the second phase, a complete system of nonlinear equations is derived based on the instruction sequence, and a discrete relaxation algorithm is proposed to solve this system of equations to derive the value solution. In the first phase, only path analysis is performed so that the complexity of searching is significantly reduced. The exact value solution is derived in the second phase and the data flow value conflicts are efficiently solved. The experimental results show that the proposed techniques are very effective and promising.
In a hierarchical test generation process, the system level functional constraints on the inputs of the module under test cause the ATPG to be inefficient. This thesis will propose both top-down and bottom-up techniques to overcome control constraints and bus constraints. The experimental results show that a very significant speedup can be achieved.
An architectural level fault simulator using symbolic data is proposed in this thesis to relieve the dependence of the complete gate level description. At the architectural level, the behavioral simulation uses symbolic data to simultaneously process the fault effects for groups of faults in the module under simulation to accelerate the process. Combined with the high level test generation techniques, this new fault simulation technique forms a complete test generation package at the architectural level. The proposed fault simulator has also been implemented, and the experimental results show that both functional tests and test vectors generated by ATPG tools can be successfully simulated on the benchmark circuits. (Abstract shortened by UMI.)
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