Floor Planning and Global Routing in an Automated Chip Design System
Hsu, Yu-Chin
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https://hdl.handle.net/2142/69580
Description
Title
Floor Planning and Global Routing in an Automated Chip Design System
Author(s)
Hsu, Yu-Chin
Issue Date
1987
Doctoral Committee Chair(s)
Kubitz, William,
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Abstract
In this thesis, a systematic approach has been taken to generating either a slicing or non-slicing structure floorplan. For non-slicing structure layout, the system is divided into initial placement, initial floorplan construction and a floorplan packing. A new analytical model is introduced for the initial placement. Unlike previous analytical methods in which modules are modeled as points, the area of each module as well as its interconnections are considered in the objective function. An energy function is defined between any two modules and the objective is to minimize the total energy. A new module packing algorithm is introduced. A novel feature of the algorithm is that modules are shifted back to obtain the maximal slack region for modules. The slack region provides useful information for reducing the critical path of the chip. For the slicing structure approach, after the initial placement, slicing and slicing structure optimization are performed. Slicing is used to obtain a slicing structure topology for the modules. It recursively bisects the initial placement result according to the area distribution. Slicing structure optimization is used to determine an optimal shape for all the modules, given the chip aspect ratio constraints. These algorithms are integrated and linked by a common database and are driven by a main program using hierarchical graphic menu entries. Experimental results show that the non-slicing structure approach achieves better area utilization and shorter wiring length than the slicing structure floorplan methodology, especially when the number of fixed-shaped modules is large.
A new path selection heuristic search algorithm is proposed for finding the minimum rectilinear tree in a rectilinear geometry graph. In the search process, the active terminals are modeled as magnets. Unlike previous search algorithms which divided a multi-terminal net connection into several independent pair connections, this algorithm considers the existence of the active terminals during the path searching process. Two commonly used tree connection algorithms were used experimentally. The algorithm is shown experimentally to be better than those produced by the other search algorithms which do not consider the active terminals. The idea of a path selection heuristic search algorithm can also be applied to a Lee-type expansion algorithm by assigning each fringe vertex x a value f(x) = g(x) $-$ i(x). The small attractive force produced by the active vertices can be precalculated by grid processors for hardware routers, so that a much faster execution speed can be obtained.
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