Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)
Yu, Meng-Lin
This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/69556
Description
Title
Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)
Author(s)
Yu, Meng-Lin
Issue Date
1986
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Abstract
A new approach is introduced for solving the automatic random logic layout synthesis problem. The emphasis is on the global optimization which requires that partitioning, placement and synthesis schemes consider the two-dimensional nature of the problem. Divide-and-conquer principle is used for partitioning the logic into small cells. The placement and wire assignment scheme propagates the structural constraints of the module to the lowest level cells. Cells are then custom-synthesized under those structural constraints by the cell synthesizer. The cell synthesizer uses one-dimensional cell structures and new efficient linear-time algorithms based on the interval graph optimization for producing an optimal layout on the virtual grid and experiments layout synthesis on virtual grids under multiple structural constraints.
The effectiveness of imposing relative I/O ordering constraints is supported by the experimental data. Routing area reduction usually more than compensates for the cell area penalty. Smaller than quadratic area growth rate for cell synthesis has been observed. Experience suggests that this approach is a viable and promising one for VLSI layout synthesis.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
