The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)
Krolikoski, Stanley Joseph
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https://hdl.handle.net/2142/69542
Description
Title
The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)
Author(s)
Krolikoski, Stanley Joseph
Issue Date
1985
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Abstract
Turn-around time is becoming a crucial problem in integrated circuit design. Thus, Programmable Logic Arrays (PLA's) have become popular means with which to implement circuits. Their regular (i.e., matrix) structure allows for easy initial design and quick changes at later stages of design. PLA's, however, waste space, and so some method for reducing them has been sought. The SQUEEZE algorithm is used in reducing PLA's. It does not guarantee the minimality of its results, but it is able to produce near minimal results in a reasonable amount of cpu time.
The thesis is divided into three main sections. First, there is an introduction to PLA's. Next there is an in-depth discussion of SQUEEZE. Finally, there are statistics presented which indicate the actual performance of the programs which implement SQUEEZE.
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