Fault Tolerance and Performance Improvement in Multiprocessor Interconnection Networks (shuffle-Exchange, Redundant-Path Array Processors)
Padmanabhan, Krishnan
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https://hdl.handle.net/2142/69532
Description
Title
Fault Tolerance and Performance Improvement in Multiprocessor Interconnection Networks (shuffle-Exchange, Redundant-Path Array Processors)
Author(s)
Padmanabhan, Krishnan
Issue Date
1984
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Abstract
A general class of fault-tolerant multistage interconnection networks is introduced, wherein fault tolerance is achieved by providing non-unique paths between each input and each output. The topology of the multiple paths is specified by means of a redundancy graph. Different techniques for constructing such networks are presented and relevant properties and control algorithms investigated. Several implementation issues, including concurrent detection of errors and effective utilization of the redundant paths, are discussed and resultant improvements in network reliability analyzed under various circumstances. Performance of the network operating in both circuit switched and packet switched modes is evaluated in detail. Redundant path networks are shown to provide significant tolerance to faults at minimal costs, as well as improvements in performance and very graceful degradation.
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