Optimization and Testing of Nmos Arithmetic Structures (Vlsi, Mos)
Montoye, Robert Kevin
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https://hdl.handle.net/2142/69520
Description
Title
Optimization and Testing of Nmos Arithmetic Structures (Vlsi, Mos)
Author(s)
Montoye, Robert Kevin
Issue Date
1984
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Abstract
Reduction in linewidths in VLSI MOS has a positive effect on the cost/performance of the technology. It both decreases the circuit delays and increases the functionality available on-chip and, as such, gives MOS the potential to become a high performance technology. In order to economically exploit this potential, structures must be automatically optimized, incorporating both system parameters such as word length and desired delay for the structure and technological constraints such as geometrical spacing rules and circuit delay characteristics. This reduces the human redesign time required to take advantages of technological improvements, allowing more complex chips to be designed at reasonable cost. Additionally, testing and concurrent error detection must be incorporated on the chip so that increased density does not drastically increase the testing costs. To obtain the increased performance, structures which reflect the strengths of the technology must be selected with their device sizes optimized to the technological (both geometrical and electrical) constraints. This Thesis develops optimization methods for structures in a carry-lookahead family and a family of new circuits for faster column compression (allowing increased performance for multiplication). Additionally, on-chip testing becomes more critical as the delays and costs of off-chip testing increase drastically with an increase in density. The problem of a on-chip tester of low complexity for a general lookahead adder is addressed. Finally, low cost (both in time and hardware) testers are described for the new compressor family both for the static (permanent) faults and dynamic (environmentally caused) faults.
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