Compilation of Register Transfer Language Descriptions Into Silicon
Bilgory, Avinoam
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https://hdl.handle.net/2142/69509
Description
Title
Compilation of Register Transfer Language Descriptions Into Silicon
Author(s)
Bilgory, Avinoam
Issue Date
1982
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Abstract
This thesis describes a design automation system for compiling high-level-language behavioral descriptions of VLSI systems into layout descriptions. The optimization goal is to generate the minimum-area layout that meets given time specifications and technological constraints. This goal is achieved by basing the system on an innovative design methodology, the most important features of which are structured design (hierarchy and regularity), intracell wiring strategy, algorithmically defined cells, and efficient handling of Register Transfer (RT) operators which are represented by Boolean recurrences.
The system uses hierarchy to partition the design into manageable parts. A great emphasis is put on regularity--both of cells and interconnections--which results in reducing the complexity of the design and the area occupied by the wires.
Interconnections are defined as part of the cell descriptions. The system guarantees that adjacent cells can be connected by abutment rather than routing, and therefore global routing is almost eliminated.
Unlike other similar systems, the system does not use a library of cells. Rather, cells are defined during the compilation process and their layouts generated algorithmically from their descriptions. Thus, each cell is tailored to the design needs and its area utilization is maximized.
Efficient algorithms are given for the handling of RT operators which are represented by Boolean recurrences (e.g., binary adders). Unlike RT vector operations, which have constant delay irrespective of the vector length n, these RT operations have delays of O(n) when implemented serially, or as small as O(log n) when implemented in parallel. However, parallel structures can be generated given any delay between these two extremes, with obvious tradeoff between time and area: the smaller the delay--the more area the structure occupies. Given any delay or area specifications, these algorithms generate the optimal layouts.
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