The Design of Programmable Logic Arrays With Concurrent Error Detection
Mak, Gong-Po Philip
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Permalink
https://hdl.handle.net/2142/69507
Description
Title
The Design of Programmable Logic Arrays With Concurrent Error Detection
Author(s)
Mak, Gong-Po Philip
Issue Date
1982
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Abstract
This research has mainly centered on the design of PLAs with concurrent error detection. The PLAs are designed to achieve the totally self-checking (TSC) goal of producing a noncode word as the first erroneous output due to a fault. Since a strongly fault secure (SFS) circuits have been shown to be the largest class of circuits that achieve the TSC goal, we concentrate on the design of SFS PLAs rather than TSC PLAs. The concept of SFS circuits is discussed and the relationship between TSC and SFS circuits is explored. The fault assumptions for SFS circuits and the necessary conditions for a circuit to be SFS under these fault assumptions are presented.
To facilitate the analysis of the faulty behavior of PLAs, a concept of representing both the AND array and the OR array by a general array is introduced. The input-output relation of this general array is expressed in a matrix form and the effect of various faults within the array can be analyzed easily. A fault model for PLAs is also introduced. In this model, physical failures in PLAs are modeled as eleven logical fault types. It is shown that any single fault of these fault types causes only unidirectional errors at the outputs of PLAs.
A very important concept called "complete covering" is introduced and proved to be absolutely necessary in designing SFS PLAs and TSC PLAs. To detect unidirectional errors in PLAs, two famous unordered codes such as the m-out-of-n code and the Berger code are used to encode the outputs of the OR array. A new code called the modified Berger code is proposed. It requires less number of check bits than the original Berger code and the m-out-of-n code, thus is very promising in the design of SFS PLAs or even TSC PLAs.
The design of code disjoint checkers for the m-out-of-n code, the two-rail code, the Berger code, and the modified Berger code are all presented. Compared with TSC checkers, they are greatly simplified because of the elimination of the TSC property. Two design procedures are presented for designing non-disjoint and disjoint SFS PLAs respectively. The former generates check bit functions for different encoding schemes, and then uses a multi-output function minimization method to generate a minimal set of product terms. The absolute minimality of the result is guaranteed. The latter generates a set of disjoint product terms by a heuristic method.
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