Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Tejayadi, Ongky
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Permalink
https://hdl.handle.net/2142/69391
Description
Title
Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Author(s)
Tejayadi, Ongky
Issue Date
1988
Doctoral Committee Chair(s)
Hajj, Ibrahim N.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Abstract
The work presented in this thesis deals with the development of a fast and fairly accurate Computer Aided Design software for simulating very-large-scale-integrated (VLSI) circuits. The methods rely on piecewise linearized nonlinear elements in the circuits.
The piecewise linear approaches explored in this work are (1) A fast piecewise linear Gauss-Seidel waveform relaxation method. (2) A slower but more accurate piecewise linear method based on simplices. (3) A Gauss-Seidel piecewise linear method with dynamic partitioning.
Also described in a mixed method which combines the fast piecewise linear method and the dynamic partitioning method. The circuit to be analyzed is partitioned into dc-connected subcircuits and then sequenced for analysis. Small subcircuits are solved using the fast piecewise linear method while large subcircuits, including the strongly-connected components in the circuit, are solved using the dynamic partitioning method.
A parallel implementation of the Gauss-Seidel piecewise linear method with dynamic partitioning on a uniprocessor computer is studied. Algorithms for the parallel implementation of the dynamic partitioning approach on a multiprocessor with shared memory (Alliant FX/8) are also explained in detail.
The piecewise linear methods presented in this work have been implemented in a set of programs called PLATINUM. The waveforms generated by PLATINUM are fairly accurate as compared to SPICE2, and the speedup for a uniprocessor machine is over two orders of magnitude, while the parallel implementation gives an additional 4 to 6 times speed improvements.
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