Switch-Level Timing Simulation of Mos Vlsi Circuits
Rao, Vasant Bangalore
This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/69310
Description
Title
Switch-Level Timing Simulation of Mos Vlsi Circuits
Author(s)
Rao, Vasant Bangalore
Issue Date
1985
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Abstract
This dissertation deals with the development of a fast and accurate simulation tool for very-large-scale integrated (VLSI) circuits of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented in this thesis can handle only n-channel MOS (NMOS) circuits, but are easily extendible to handle complementary MOS (CMOS) circuits as well.
An NMOS circuit is modeled as a set of nodes connected by transistor switches. Three strengths and three states are used to represent the signals at the nodes in the circuit. The strengths in decreasing order are input, pullup and normal. The three states used are 0, u, and 1 with 0 and 1 representing the conventional low and high signal values respectively while the u state is used to represent intermediate signal values and sometimes to represent situations of conflict. Each switch is either open, closed, or in an intermediate state.
The enhancement transistors in the NMOS network are first partitioned into driver and pass transistors. The NMOS network itself is then partitioned into multifunctional blocks (MFB), pass transistor blocks (PTB), and input sources (SRC). The partitioning is an automatic process that is completely transparent to the user and can be performed in linear time. The partitioned blocks are then ordered for processing so that, whenever possible, a block is scheduled for processing only after all its inputs have been previously processed. Since this is not possible for blocks forming feedback, loops, a novel dynamic windowing scheme is used to schedule such blocks.
The blocks in the partitioned network are then simulated at the switch level using graph algorithms, producing so-called, zero-delay ternary signal waveforms. The zero-delay signal transitions are then delayed by using delay and filtering operators. The characteristics of the delay operator are computed in a presimulation phase by simulating five different circuit primitives using an accurate circuit simulator such as SPICE2. These characteristics are stored in a table. During the simulation a circuit block is mapped onto one of the five primitives and appropriate delay values are obtained by fast table lookup techniques. Several factors such as block configuration, loading, device geometries, and input slew rates are taken into account while computing the delay values.
The algorithms presented in this thesis have been implemented in a computer program called MOSTIM. In all the circuits simulated thus far, MOSTIM provides timing information with an accuracy of within 10% of that provided by SPICE2, at approximately two orders of magnitude faster in simulation speed.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
