Modeling and Extraction of Interconnect Parameters in Very-Large-Scale Integrated Circuits
Yuan, Chen-Ping
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https://hdl.handle.net/2142/69278
Description
Title
Modeling and Extraction of Interconnect Parameters in Very-Large-Scale Integrated Circuits
Author(s)
Yuan, Chen-Ping
Issue Date
1983
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Abstract
The increased complexity of the very large scale integrated circuits (VLSI) has greatly impacted the field of computer-aided design (CAD). One of the problems brought about is the interconnection problem.
In this research, the goal is twofold. First of all, a more accurate numerical method to evaluate the interconnect capacitance, including the coupling capacitance between interconnects and the fringing field capacitance, was investigated, and the integral method was employed. Two FORTRAN programs "CAP2D" and "CAP3D" based on this method were developed. Second, a PASCAL extraction program emphasizing the extraction of interconnect parameters was developed. It employs the "cylindrical approximation formula" for the self-capacitance of a single interconnect and other simple formulas for the coupling capacitances derived by a "least square method". The extractor assumes only Manhattan geometry and NMOS technology. Four-dimensional binary search trees are used as the basic data structure.
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