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https://hdl.handle.net/2142/66458
Description
Title
A Study of Nor/nand Networks
Author(s)
Alkhateeb, Deyaa Lutfi Karim
Issue Date
1981
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
Designing logic networks with a mixture of NOR and NAND gates is of significant importance. One major reason is that most logic families are capable of realizing both NOR and NAND functions easily. Despite the importance of NOR/NAND networks, we can hardly find publications discussing the subject. In Part I of this thesis, we discuss the design of NOR/NAND networks. The conditions of the redundancy of gates and connections are derived together with other properties of NOR/NAND networks. These properties are used to develop the integer programming logic design ILLOD-NOR/NAND-B program. This program is developed to design optimal NOR/NAND networks under different restrictions such as fan-in, fan-out, or level restrictions. The program can handle both single- and multiple-output functions either completely or incompletely specified.
In Part II, we discuss the design of optimal parallel binary adders using a mixture of NOR and NAND gates. Optimal networks for the parallel binary adder with an arbitrary bit length have been difficult to generate, because of the large number of gates involved. Nevertheless, optimal one-bit full adders can be generated using the integer programming logic design method. Carry-ripple adders which are a cascade of optimal one-bit full adders, however, are not guaranteed to be optimal. In this part, we obtain optimal parallel binary adder networks under different criteria of optimization. The optimal networks obtained have fewer gates, fewer connections, and/or shorter gate delays than conventional parallel binary adders which are a cascade of optimal one-bit full adders.
In Part III, we discuss the design of parallel multipliers using a mixture of NOR and NAND gates. In this part, we discuss a parallel multiplication scheme that uses 2 x 2 multipliers in generating the partial products, i.e., the summand matrix. Characteristics of the generated summand matrix are discussed and a suitable summation scheme is presented. The new scheme uses less gates than other known conventional schemes. Extensions of the scheme to accommodate two's complement multiplication are also presented.
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