Ring Oscillator Integrator Based Analog Filter: System Level Design and Modeling Using Verilog-AMS

Zhu, Junheng

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https://hdl.handle.net/2142/55664 Copy

Description

Title

Ring Oscillator Integrator Based Analog Filter: System Level Design and Modeling Using Verilog-AMS

Author(s)

Zhu, Junheng

Contributor(s)

Hanumolu, Pavan Kumar

Issue Date

2014-05

Keyword(s)

• Analog filters
• analog signal processing
• continuous time filters
• integrator
• ring oscillator
• ring oscillator integrator

Abstract

Filters are important building blocks in many analog signal processing systems. Traditional filter implementation involves the applications of two commonly used analog integrators, the Gm-C integrator and the Opamp-RC integrator. The DC gain of the two conventional analog integrators are greatly limited by the gain of the operational amplifier (Opamp) used in the Opamp-RC integrator or operational transconductance amplifier (OTA) used in the Gm-C integrator. Furthermore, process scaling of technology available for integrated circuits is beneficial for smaller area and higher density of integrated circuits yet inevitably reduces the output impedance of the transistors, therefore further exacerbating the performance of Opamp and OTA. This thesis features applying ring oscillator integrators (ROIs) in the design of analog. ROIs implemented using simple CMOS inverters can achieve infinite DC gain at low supply voltage independent of transistor non-idealities and imperfections such as the finite output impedance. Consequently, ROI based analog filter design scales more effectively into newer technology processes. The project starts with an overview of background theory of analog filter design, followed by high order analog filter topologies constructed based on Opamp-RC integrators along with system-level behavioral simulations using MATLAB focusing on second order filters. In the second part, ROI based analog filter design is proposed with system-level analysis. The suggested filter topology is then verified by system-level Verilog-AMS simulation for first order and second order analog filter design. In the third part, we will implement our proposed ROI analog filter at circuit-level using 180 nm TSMC models. We then verify and analyze the performance of ROI analog filter with Cadence Virtuoso. Finally, we conclude our project with a summary and evaluation of the research results and suggestions of possible future research and improvements of our project.

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/55664

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