Design Error Localization Using Simulation Guided Weakest Precondition
Li, Yandong
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https://hdl.handle.net/2142/55329
Description
Title
Design Error Localization Using Simulation Guided Weakest Precondition
Author(s)
Li, Yandong
Contributor(s)
Vasudevan, Shobha
Issue Date
2014-05
Keyword(s)
bug localization
weakest precondition
EDA
Abstract
Automated design error localization is essential in debugging aids.
Hardware
design, like ASICs, has been evolving rapidly and getting more and
more complex. The consequence is the increasing difficulty in pre-silicon
debugging. There is a great need from the EDA community for a better
design aid tool to automize the debugging process. Some previous studies
have proposed various statistical analysis methods for bug localization, but
the disadvantage of these methods are the scalability and their results depend largely on the quality of input design assertions. We propose a new
bug localization method based on weakest liberal precondition. It combines
the basic weakest liberal precondition computation with the guidance of a
concrete execution path to increase the scalability. The experiment on an
eight-entry synchronous FIFO example shows the capability of narrowing
down to two lines of buggy codes after we intentionally injected a constant
replacement error at the initialization stage.
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