This item is only available for download by members of the University of Illinois community. Students, faculty, and staff at the U of I may log in with your NetID and password to view the item. If you are trying to access an Illinois-restricted dissertation or thesis, you can request a copy through your library's Inter-Library Loan office or purchase a copy directly from ProQuest.
Permalink
https://hdl.handle.net/2142/47065
Description
Title
Hybrid Prefetcher
Author(s)
Venshtain, Simion
Issue Date
2008-12
Keyword(s)
computer memory
prefetching
hardware prefetching
computer architecture
Abstract
In the last century great progress was achieved in developing processors with extremely high computational capabilities. However, one of the biggest suppressors of those capabilities is the memory subsystem. Many approaches are used to bypass this constraint. Some took the approach of parallelism, while others use cache optimizations to minimize memory latency. An additional approach, and the one I will elaborate in this paper, is prefetching. In this paper I will only talk about hardware prefetching, which relies on additional hardware to preform prefetching and is preformed during runtime. In my prefetcher design I try to deliver the best memory access pattern recognition, while minimizing the impact on memory bandwidth and cache pollution. To achieve this I created a hybrid between a correlated prefetcher and a stride prefetcher. Since both approaches have their advantages and disadvantages, I tried to achieve a design that will help mask the disadvantages and expose the advantages of both approaches. Also, I utilized a more calculated approach rather than brute force to perfom the necessary prefetches.
Use this login method if you
don't
have an
@illinois.edu
email address.
(Oops, I do have one)
IDEALS migrated to a new platform on June 23, 2022. If you created
your account prior to this date, you will have to reset your password
using the forgot-password link below.
