Fcuda Memory Subsystems

Xu, Shuotao

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https://hdl.handle.net/2142/46511 Copy

Description

Title

Fcuda Memory Subsystems

Author(s)

Xu, Shuotao

Contributor(s)

Chen, Deming

Issue Date

2012-05

Keyword(s)

• computer memory
• parallel processing
• CUDA
• field-programmable gate arrays

Abstract

FCUDA is an innovative design flow, which transforms high-level parallel codes for GPUs into FPGA configurations for higher performance and lower power consumption. FCUDA is a joint project involving multiple research groups including the ECE department of University of Illinois at Urbana-Champaign (Deming Chen and Wen-Mei Hwu’s groups), the CS department of University of California at Los Angeles (Jason Cong’s group), and ADSC (Advanced Digital Science Center) in Singapore. The research task was to design customizable and lightweight high-bandwidth memory communication subsystems that connect multiple custom cores instantiated on the FPGA device to the off-chip DDR2 memory. Achieving high bandwidth for FPGA devices is especially challenging due to fewer memory channels compared to GPU and CPU. Meanwhile, the current standard bus systems offered by FPGA vendors are associated with high delay and area overhead due to the support of reconfigurability; thus these systems cannot deliver high-speed data transfers. The first part of the work is to modify the existing modules of DDR2 memory controller generated by Xilinx ISE tool to interface with FCUDA-generated cores. In order to overcome an intrinsically fixed burst length of a standard memory controller, a module enables a sequential burst of burst to support high-performance parameterizable memory transfers are then designed. Data alignment is paid special attention when large amount datum bursted.

Type of Resource

text

Language

en

Permalink

http://hdl.handle.net/2142/46511

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