Exploiting application level error resilience via deferred execution
Duwe, Henry
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https://hdl.handle.net/2142/44189
Description
Title
Exploiting application level error resilience via deferred execution
Author(s)
Duwe, Henry
Issue Date
2013-05-24T21:53:46Z
Director of Research (if dissertation) or Advisor (if thesis)
Kumar, Rakesh
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
approximate computing
low energy computing
Abstract
Many programs exhibit application level error resilience which allows certain subcomputations to execute in an imprecise, yet energy efficient manner, potentially yielding significant overall energy savings without sacrificing end- to-end quality. In this thesis we identify one fundamental problem that must be addressed to realize these energy benefits: even in applications with a large degree of error resilience, error resilient instructions are interleaved with instructions that must be executed precisely at a fine-grained level (about every seven instructions). This interleaving prohibits any energy savings due to the significant costs associated with switching between the modes, typically via voltage scaling, which may require hundreds to thousands of cycles to transition between levels. We propose a novel execution model for single-core architectures that reduces total switching by deferring execution of instructions requiring mode switches, thereby aggregating instructions of the same energy mode and reducing the number of mode switches. Deferred execution introduces overheads of its own due to data transfer across the two modes, and we present hardware and software optimizations to mitigate these overheads, yielding up to 9%-29% energy savings across a suite of benchmarks.
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