Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)

Bhagat, Karan

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https://hdl.handle.net/2142/42300 Copy

Description

Title

Tutorial on designing and implementing a direct digital synthesizer (DDS) on a field programmable gate array (FPGA)

Author(s)

Bhagat, Karan

Issue Date

2013-02-03T19:30:47Z

Director of Research (if dissertation) or Advisor (if thesis)

Schutt-Ainé, José E.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• direct digital synthesis (DDS)
• direct digital synthesizer
• direct digital synthesizer (DDS)
• Field-Programmable Gate Array (FPGA)
• circuit design
• digital circuit design
• design flow
• design
• Implementation
• Verilog
• tutorial
• phase accumulator
• sine lookup table
• phase truncation
• spurs
• simulation
• place and route
• ModelSim
• Xilinx
• Virtex

Abstract

Many telecommunication applications require a fast switching, fine tuning and superior quality sinusoidal signal source for their components. One such a frequency synthesizer is a direct digital synthesizer (DDS). This thesis work utilizes a design that aims to combine digital circuit design and electronic communication knowledge, and apply them in a practical environment. It does so by providing a tutorial on designing and implementing a DDS on an FPGA using Xilinx’s ISE software. The thesis also examines the final results and shows the unwanted spurs that are generated. Since this is purely a digital design, it does not implement a digital-to-analog converter (DAC) or a low-pass filter. Using a Virtex 6 design for the FPGA, one can achieve close to perfect sinusoids, without any phase change, with varying frequency tuning words (FTWs).

Graduation Semester

2012-12

Permalink

http://hdl.handle.net/2142/42300

Copyright and License Information

Copyright 2012 Karan Bhagat

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