Director of Research (if dissertation) or Advisor (if thesis)
Shanbhag, Naresh R.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Date of Ingest
2012-09-18T21:18:12Z
Keyword(s)
Minimum Energy Operation Point (MEOP)
Dynamic Voltage Scaling (DVS)
Compute Voltage Regulator Module (VRM)
Continuous Voltage-Frequency Scaling (CVFS)
Critical Path Replica (CPR)
Abstract
Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to meet timing constraints. In this work, we observe that static CMOS is robust under low supply voltages, operates reliably during voltage transients, and exhibits similar voltage-delay characteristic across logic families. We present a continuous voltage-frequency scaling (CVFS) approach where supply variation is relaxed, and timing violations are avoided through the use of on-chip clock generation. A simple model of the critical path is presented to track circuit behavior in real time. This approach presents small overhead in data transition but enables energy optimization at the system-level. The contribution of this thesis includes the design of the digital blocks for a prototype chip in IBM 130nm technology.
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