Programmable stochastic processors

Sartori, John

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https://hdl.handle.net/2142/34410 Copy

Description

Title

Programmable stochastic processors

Author(s)

Sartori, John

Issue Date

2012-09-18T21:15:34Z

Director of Research (if dissertation) or Advisor (if thesis)

Kumar, Rakesh

Doctoral Committee Chair(s)

Kumar, Rakesh

Committee Member(s)

• Shanbhag, Naresh R.
• Patel, Janak H.
• Kahng, Andrew B.
• Austin, Todd

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• stochastic computing
• energy efficiency
• error tolerance
• computer-aided design
• computer architecture
• binary optimization

Abstract

As traditional approaches for reducing power in microprocessors are being exhausted, extreme power challenges call for unconventional approaches to power reduction. Recent research has shown substantial promise for application-specific stochastic computing, i.e., computing that exploits application error tolerance to enable careful relaxation of correctness guarantees provided by hardware in order to reduce power. This dissertation explores the feasibility, challenges, and potential benefits of stochastic computing in the context of programmable general purpose processors. Specifically, the dissertation describes design-level techniques that minimize the power of a processor for a non-zero error rate or allow a processor to fail gracefully when operated over a range of non-zero error rates. It presents microarchitectural design principles that allow a processor to trade off reliability and energy more efficiently to minimize energy when exploiting error resilience. It demonstrates the benefit of using compiler optimizations that optimize a binary to enable more energy savings when operating at a non-zero error rate. It also demonstrates significant benefits for a programmable stochastic processor prototype that improves energy efficiency by carefully relaxing correctness and exposing errors in applications running on a commodity processor. This dissertation on programmable stochastic processors conclusively shows that the architecture and design of processors and applications should be approached differently in scenarios where errors are allowed to be exposed from the hardware to higher levels of the compute stack. Significant energy benefits are demonstrated for design-, architecture-, compiler-, and application-level optimizations for general purpose programmable stochastic processors.

Graduation Semester

2012-08

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http://hdl.handle.net/2142/34410

Copyright and License Information

Copyright 2012 John M. Sartori

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