Clock tree synthesis under aggressive buffer insertion
Chen, Ying-Yu
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https://hdl.handle.net/2142/34230
Description
Title
Clock tree synthesis under aggressive buffer insertion
Author(s)
Chen, Ying-Yu
Issue Date
2012-09-18T21:06:58Z
Director of Research (if dissertation) or Advisor (if thesis)
Chen, Deming
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Clock Tree
Buffer Insertion
Buffer Sizing
Maze Routing
Slew
Abstract
In this thesis, we propose a maze-routing-based clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree topology, our proposed algorithm has more freedom and thus achieves more robust slew control. Buffer insertion along routing paths had been mostly avoided previously due to the difficulty of maintaining a low skew under such aggressive buffer insertion. We developed an accurate timing analysis engine for delay and slew estimations and a balanced routing scheme for better skew reduction during clock tree synthesis. As a result, we can perform aggressive buffer insertion and maintain accurate delay information and low skew. Buffer sizing is also guided by its performance for slew control. Experiments show that our synthesis results not only honor the slew constraints but also maintain reasonable skew.
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