Charged device model electrostatic discharge protection and test methods for integrated circuits

Jack, Nathan

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https://hdl.handle.net/2142/30911 Copy

Description

Title

Charged device model electrostatic discharge protection and test methods for integrated circuits

Author(s)

Jack, Nathan

Issue Date

2012-05-22T00:14:40Z

Director of Research (if dissertation) or Advisor (if thesis)

Rosenbaum, Elyse

Doctoral Committee Chair(s)

Rosenbaum, Elyse

Committee Member(s)

• Cangellaris, Andreas C.
• Schutt-Ainé, José E.
• Shanbhag, Naresh R.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• electrostatic discharge
• charged device model
• transmission line pulsing
• wafer-level CDM (WCDM)
• ESD test methods
• IC reliability
• charged device model (CDM)
• electrostatic discharge (ESD)
• field-induced CDM (FICDM)
• WCDM2
• capacitively coupled TLP (CC-TLP)
• Transmission line pulsing (TLP)
• very-fast transmission line pulsing (VF-TLP)
• integrated circuits (ICs)

Abstract

This work focuses on methods for testing and increasing the robustness of integrated circuits (ICs) to electrostatic discharge (ESD). Specifically, this work focuses on charged device model (CDM) protection and test methods. In this work it is shown that the CDM robustness of an I/O can be increased by proper biasing of the gates during an ESD event. These gate bias networks are particularly useful because they do not add capacitance to high-speed nodes. The effectiveness of diode vs. diode-triggered silicon controlled rectifier (DTSCR) protection in high-speed I/O cells is examined. The industry standard for CDM characterization of a product is field-induced CDM (FICDM) testing of packaged ICs. However, several wafer-level CDM testers have also been introduced, including very-fast transmission line pulsing (VF-TLP) and capacitively coupled TLP (CC-TLP). This work presents three new wafer-level CDM testers. Two are modifications of existing CC-TLP and “WCDM” testers. The modified testers allow one to probe internal nodes during the stress event. The third, named “WCDM2,” is an improvement upon WCDM. The merits and drawbacks of each of these testers are examined in this work. Primarily, this work seeks to methodically answer the outstanding question of whether or not wafer-level CDM testing can replicate FICDM stress. An embeddable voltage monitor circuit is presented that is capable of recording for subsequent readout the peak voltage reached at internal nodes during ESD events. Techniques for probing internal nodes during CDM-like events are also presented. Using these and other techniques, fatal and non-fatal stress generated within two CDM test chips by the various CDM testers are compared to each other. It is shown that wafer-level testing does not replicate FICDM stress in various scenarios.

Graduation Semester

2012-05

Permalink

http://hdl.handle.net/2142/30911

Copyright and License Information

Copyright 2012 Nathan Jack

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