SHA-less pipeline ADC design with sampling clock skew calibration

Huang, Pingli

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https://hdl.handle.net/2142/29565 Copy

Description

Title

SHA-less pipeline ADC design with sampling clock skew calibration

Author(s)

Huang, Pingli

Issue Date

2012-02-01T00:55:42Z

Director of Research (if dissertation) or Advisor (if thesis)

Chiu, Yun

Committee Member(s)

• Feng, Milton
• Rosenbaum, Elyse
• Wong, Martin D.F.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Sample-and-hold amplifier (SHA)
• SHA-less
• pipelined ADC
• multi-bit pipeline architecture
• sampling clock skew
• skew calibration.
• analog-to-digital converters (ADCs)

Abstract

The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the sampling clock skew between the sub-ADC and the multiplying digital-to-analog converter (MDAC) in the pipeline first stage results in gross conversion errors at high input frequencies. This skew effect is aggravated in a SHA-less multi-bit-per-stage pipeline architecture, where the built-in redundancy is limited. Sampling clock skew is an essential problem in SHA-less pipeline ADCs that prohibits their use at high input frequency applications. In this thesis, a mostly digital background calibration technique is developed to remove the sampling clock skew in SHA-less pipeline ADCs. The skew information is extracted from the first-stage residue output with two comparators sensing out-of-range errors; a gradient-descent algorithm is used to adaptively adjust the timing of the sub-ADC to synchronize with that of the sample-and-hold (S/H) in the MDAC. A prototype 10-bit, 100-MS/s SHA-less pipeline ADC incorporating this calibration technique was designed and fabricated in 90-nm CMOS process. The prototype ADC converts from DC to the 12th Nyquist band with a 3.5-bit front-end stage. It digitizes inputs up to 610 MHz without skew errors in experiments; in contrast, the same ADC fails at 130 MHz with calibration disabled. The calibration circuits were fully integrated on chip. The ADC consumes 12.2 mW and occupies 0.26-mm2 silicon area, while the calibration circuits dissipate 0.9 mW and occupy 0.01 mm2. A 71-dB spurious-free dynamic range (SFDR) and a 55-dB signal-to-noise-and-distortion ratio (SNDR) were measured with a 20-MHz sine-wave input, and a larger than 55-dB SFDR was measured in the 10th Nyquist band.

Graduation Semester

2011-12

Permalink

http://hdl.handle.net/2142/29565

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COPYRIGHT 2011 PINGLI HUANG

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