FPGA-based digital phase-locked loop analysis and implementation
Hu, Dan
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https://hdl.handle.net/2142/24165
Description
Title
FPGA-based digital phase-locked loop analysis and implementation
Author(s)
Hu, Dan
Issue Date
2011-05-25T15:08:34Z
Director of Research (if dissertation) or Advisor (if thesis)
Schmitz, Christopher D.
Franke, Steven J.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
digital Phase-locked loop (PLL)
Field Programmable Gate Array (FPGA)-based implementation
Direct Digital Synthesizer (DDS)
Abstract
The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to synthesize analog output, the frequency of which is controlled digitally by the FPGA. This system is implemented in a way that makes it educational and suitable for a lab module. Unlike purely digital PLL, this project involves several analog circuits soldered on PCBs, which will help the students visualize the signal flow in the PLL and get some exposure to mixed-signal systems.
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