Cache design exploration in a general purpose massively parallel architecture
Venshtain, Simion
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https://hdl.handle.net/2142/24258
Description
Title
Cache design exploration in a general purpose massively parallel architecture
Author(s)
Venshtain, Simion
Issue Date
2011-05-25T14:51:03Z
Director of Research (if dissertation) or Advisor (if thesis)
Patel, Sanjay J.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Cache
Interconnect
Cache design
Cache hierarchy
Nonblocking cache
RTL design exploration
register transfer level (RTL)
Rigel
Massively parallel
Accelerator
Abstract
Memory model design is a major part of any modern processor architecture. There
are many design choices and tradeoffs to be considered, and these often need to be
tightly coupled to the processing unit's arcitecure. The increased popularity of
massively parallel architectures has motivated researchers to further examine
the memory model tradeoffs these types of architectures and their target
applications present. This thesis will focus on Rigel, a 1024-core, general
purpose massively parallel architecure. I will study the memory model design
tradeoffs of the Rigel cluster, a subblock of the Rigel architecure, and
attempt to propose a design configuration that is suitable to the unique
requirements of the Rigel architecture. Rigel is an agressive design target
and requires us to focus on the area and power impact of the memory model
design choices. As a result, to study the design tradeoffs, I use an approach
that utlizes an RTL implementation, combined with a custom design exploration
flow built on top of production quality CAD tools. This flow allows us to extract
accurate power and area results for each design point and pick points
that provide us with the highest perfomance density.
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