Charged device model electrostatic discharge failures in system on a chip and system in a package designs

Olson, Nicholas A.

Permalink

https://hdl.handle.net/2142/24101 Copy

Description

Title

Charged device model electrostatic discharge failures in system on a chip and system in a package designs

Author(s)

Olson, Nicholas A.

Issue Date

2011-05-25T14:50:54Z

Director of Research (if dissertation) or Advisor (if thesis)

Rosenbaum, Elyse

Doctoral Committee Chair(s)

Rosenbaum, Elyse

Committee Member(s)

• Feng, Milton
• Shanbhag, Naresh R.
• Schutt-Ainé, José E.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• Charged Device Model
• Charged Device Model (CDM)
• Electrostatic Discharge (ESD)
• Electrostatic Discharge
• System on a Chip
• System in a Package

Abstract

Advances in integrated circuit design and packaging techniques have introduced new ESD-susceptible (Electrostatic Discharge) circuit interfaces. This document will introduce these interfaces and the methods that were used to investigate their ESD robustness. Two test chips were designed to aid the analysis. The specialized design choices that allow for distinguishing between multiple failure locations are thoroughly illustrated. The testing plan is detailed and the test chip measurement results are analyzed. The results will compare different ESD protection techniques and illustrate the importance of having ESD protection at these interfaces. The results will also show how some interfaces are inherently more robust than others during a CDM (Charged Device Model) event. Finally, the effects on the intensity of the CDM stress based on single-die or stacked-die packages will be compared.

Graduation Semester

2011-05

Permalink

http://hdl.handle.net/2142/24101

Copyright and License Information

Copyright 2011 Nicholas A. Olson

Owning Collections