An evaluation framework for massively parallel accelerator processors
Johnson, Daniel R.
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https://hdl.handle.net/2142/24396
Description
Title
An evaluation framework for massively parallel accelerator processors
Author(s)
Johnson, Daniel R.
Issue Date
2011-05-25T14:38:59Z
Director of Research (if dissertation) or Advisor (if thesis)
Patel, Sanjay J.
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Keyword(s)
Accelerator
Chip Mulitprocessor
Parallel Processing
Abstract
In this thesis, I describe the evaluation framework for Rigel,
a 1024-core single-chip accelerator architecture designed for
high throughput on visual computing and scientific workloads.
I present an integrated evaluation framework for investigating co-designed
architecture, compilers, programming models, and RTL implementation
for massively parallel chip multiprocessors (CMPs).
The research objective of the Rigel project,
designing a prototype thousand-core chip,
led to the development of the framework presented in this thesis.
I describe the tools and techniques which enabled this work.
The goal of this thesis is not to evaluate specific design tradeoffs, but to
describe the tools we have developed for making these decisions.
I motivate and describe our integrated performance simulator, code generator,
and RTL implementation for evaluation of a novel 1024-core accelerator architecture.
I demonstrate the utility of a flexible hardware-software interface
supporting an evolving ISA for architectural design space exploration.
Although I present experiences related to a particular design,
the methods applied and lessons learned are more broadly applicable.
I summarize some of the published work which this framework has enabled.
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