Exploiting multiprocessor memory hierarchies for operating systems
Xia, Chun
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https://hdl.handle.net/2142/23801
Description
Title
Exploiting multiprocessor memory hierarchies for operating systems
Author(s)
Xia, Chun
Issue Date
1996
Doctoral Committee Chair(s)
Torrellas, Josep
Department of Study
Engineering, Electronics and Electrical
Computer Science
Discipline
Engineering, Electronics and Electrical
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Computer Science
Language
eng
Abstract
With the increasing gap between processor speed and memory speed, a sophisticated memory hierarchy is key to high performance. However, the operating system tends to use the memory hierarchy poorly. This thesis presents a comprehensive characterization and optimization of the performance of multiprocessor memory hierarchies for operating systems. The operating system instruction cache misses are reduced by 81% using a code reorganization scheme tailored to the operating system, guarded sequential prefetching, and stream buffers. The operating system data cache misses are reduced by 53% using a DMA-like pipelined block transfer engine, a selective update protocol, data relocation and privatization, and data prefetching in miss hot spots. The overall OS time is reduced by 32%. The cost-performance trade-offs of the software/hardware optimization schemes are also discussed.
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