A gate-level simulator for alpha-particle-induced transient faults
Cha, Hungse
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https://hdl.handle.net/2142/23457
Description
Title
A gate-level simulator for alpha-particle-induced transient faults
Author(s)
Cha, Hungse
Issue Date
1994
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Engineering, Electronics and Electrical
Discipline
Engineering, Electronics and Electrical
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Mixed analog and digital mode simulators have been available for accurate alpha-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. This thesis describes a fast transient fault simulator which can evaluate the effects of alpha-particle hits or single event upsets (SEUs) in CMOS standard cell based synchronous sequential VLSI circuits. The speed comes from approximating the initial analog effects with gate level models, as well as using an improved transient fault simulation algorithm in a hierarchy of simulators. The simulator is shown to be between four to five orders of magnitude faster than a very accurate circuit simulator at the expense of some accuracy and some limitations on the types of circuits simulatable.
Using this simulator, benchmark circuits have been tested for their behavior under alpha-particle injections. The experiments show that the one bit flip model is not a good model for injecting faults in highly fault tolerant systems. The experiments also show that at the pin level, no simple model exists which can mimic the behavior of the circuit hit with alpha particles.
The simulator's usefulness is also shown in the development of a transient pulse tolerant D flip-flop (DFF). The tool is used to demonstrate the tradeoff between transient pulse tolerance and latch performance.
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