Linearity improvement technique for CMOS continuous-time filters
Moon, Un-Ku
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Permalink
https://hdl.handle.net/2142/23151
Description
Title
Linearity improvement technique for CMOS continuous-time filters
Author(s)
Moon, Un-Ku
Issue Date
1994
Doctoral Committee Chair(s)
Song, Bang-Sup
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Physics, Electricity and Magnetism
Physics, Condensed Matter
Language
eng
Abstract
A linearity improvement technique using a combination of passive resistors and current-steering MOS transistors as a variable resistance element is applied in the implementation of low-distortion continuous-time filters in complementary metal-oxide-semiconductor (CMOS) technology. This work is motivated by the fact that to date, most of the techniques in continuous-time, electronically tunable filters perform quite poorly in linearity. The proposed technique relies on the linearity of the passive resistors and the tunability of the current-steering MOS transistors operating in the triode region. By novel application of systematic feedback loops and by placing the nonlinear elements inside the feedback, the distortion resulting from the nonlinear devices is greatly reduced by the filter loop gain. Theoretical and experimental results, in agreement, show a significant improvement in linearity. For an audio-band (22-kHz) fifth-order Bessel filter implementation, linearity better than $-$90 dB THD is demonstrated given a 2 kHz, 4 $V\sb{p-p}$ signal in a 5-V system. The filter implementation includes a simple and novel automatic frequency-tuning method, which employs a switched-capacitor reference resistor instead of applying a conventional phase-locked loop technique or its variations. Also included in the filter implementation is a linear programming approach to optimize the dynamic range, under the constraint of a fixed capacitor area that is assumed to be the dominant factor in the total chip area.
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