Low-power giga-bit per second optoelectronic integrated circuits for two-dimensional smart-pixel arrays
Chang, Wei-Heng
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https://hdl.handle.net/2142/22637
Description
Title
Low-power giga-bit per second optoelectronic integrated circuits for two-dimensional smart-pixel arrays
Author(s)
Chang, Wei-Heng
Issue Date
1996
Doctoral Committee Chair(s)
Feng, Milton
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Optical interconnects provide wide bandwidth, low loss, and high fanout as compared to traditional electrical interconnects. In the past years many high performance optoelectronic circuits have been demonstrated. However, most of them require complicated process and exotic devices. In order to make optical interconnects in real system and commercial use, circuits utilizing manufacturable, robust, and low-cost technology have to be realized. Ion implanted GaAs MESFETs provide great promise due to their simplicity in manufacturing and their high speed performance. The optical characteristics of GaAs materials also make this technology favorable in realizing low-cost, high-performance OEICs.
By the use of advanced device modeling, circuit design, semiconductor fabrication, and high-speed characterization, we have successfully demonstrated 10 GHz OEIC receivers implemented by in-house 50 GHz 0.25 $\mu$m ion-implanted depletion-mode GaAs MESFETs. This demonstration proves that ion-implanted GaAs MESFET technology is able to provide a high level of integration and more than 15 Gb/s of operation.
Based on the experience obtained in the successful implementation of the 10 GHz receivers and motivated by the increasing demand for highly parallel optical interconnects, high-performance two-dimensional 4 x 4 and 8 x 8 smart-pixel arrays utilizing Vitesse's HGaAs-III 0.6 $\mu$m E/D MESFET process have been developed. The main design goals are aggregated data rates of 16 and 64 Gb/s (at 1 Gb/s/channel for 4 x 4 and 8 x 8 arrays), power consumption of 100 mW/channel, and sensitivity of better than $-$20 dBm. To make the data transmission transparent, fully dc-coupled circuits are designed. Obstacles in array implementation are also solved, by the novel design of the fully differential optical receivers. Approximately 5,000 and 20,000 active devices are integrated in the 4 x 4 and 8 x 8 arrays, respectively. They are by far the most complicated and densely integrated GaAs OEIC circuits. The simulated results of the complete circuits show that the design goals of low power, high speed, high density, high sensitivity, high process and power supply tolerance are met. The concepts and the design methodologies generated in the development of such circuits are expected to have an impact on the future generations of OEIC chips.
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