Hierarchical electromigration reliability diagnosis for ULSI interconnects
Teng, Chin-Chi
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Permalink
https://hdl.handle.net/2142/22614
Description
Title
Hierarchical electromigration reliability diagnosis for ULSI interconnects
Author(s)
Teng, Chin-Chi
Issue Date
1996
Doctoral Committee Chair(s)
Kang, Sung Mo
Department of Study
Engineering, Electronics and Electrical
Discipline
Engineering, Electronics and Electrical
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Electromigration is the phenomenon of metal ion mass transport along the grain boundaries when a metallic interconnect is stressed under high current density. In recent years, the line width of ULSI interconnects has been shrunk into the submicron regime. This gives rise to serious concerns about electromigration-induced failures.
To design an electromigration-reliable chip, a CAD tool that can provide the accurate worst-case electromigration reliability analysis is required. However, computing the worst-case electromigration reliability index, such as mean time-to-failure (MTF), for a single interconnect in a digital circuit is an NP-complete problem. It is even worse to consider all interconnects since so many interconnects exist in the entire circuit. In this research, a hierarchical electromigration reliability diagnosis method, which provides a feasible solution to this complicated problem, was proposed. The proposed electromigration diagnosis method uses two levels of diagnoses. The top of the hierarchy is an input pattern-independent electromigration diagnosis procedure. It can quickly identify those critical interconnects with potential electromigration reliability problems and the corresponding input patterns which cause the worst-case current stress to each critical interconnect; thus, the problem size of the worst-case electromigration diagnosis is significantly reduced and becomes tractable.
Thereafter, designers can focus on the critical interconnects and feed those critical input patterns into a pattern-dependent electromigration-reliability simulation tool, iTEM, to compute the accurate electromigration-induced failure of the interconnect systems. One important feature of iTEM is that, in addition to the current density and interconnect geometry, it takes into account the steady-state temperature of every interconnect under the given operating condition. In a state-of-the-art chip, the temperature of the interconnect may result in a rise tens of degrees above the ambient due to Joule heating and heat conduction from the substrate. Neglecting the temperature effect on electromigration-induced failure can lead to intolerable prediction errors.
Our electromigration diagnosis method combines the advantages of both the input pattern dependent and independent reliability diagnoses. This top-down approach not only handles large circuit layouts containing tens of thousands of transistors and interconnects even on a workstation, but also gives an accurate worst-case electromigration reliability estimation.
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