A unified approach for assessing circuit and packaging technologies in a system environment
Gura, Carol V.
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Permalink
https://hdl.handle.net/2142/22531
Description
Title
A unified approach for assessing circuit and packaging technologies in a system environment
Author(s)
Gura, Carol V.
Issue Date
1990
Doctoral Committee Chair(s)
Abraham, Jacob A.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Several important aspects are present in any unified approach to evaluating future technologies and packaging alternatives in a system environment. These include how to link the architecture of the system to the physical system design, how to model the devices and interconnections, how to realistically predict system size, and how to measure the length of the interconnections. In this thesis we consider these four aspects of a unified system approach to assessing technology and packaging alternatives in a system environment.
We utilize Rent's rule, a pin or terminal versus block relationship, to link the architecture to the physical system. We show that it is possible to characterize a system as a hierarchical set of packages, each package level being composed of blocks or packages from the previous packaging level.
The high speed characteristics of interconnections and packaging are needed to reliably evaluate future technologies and packaging alternatives. We show that it is better to have a more general delay model than to have a specific model which does not hold under all conditions. We derive an improved method for the transient analysis of single RLC transmission lines based on the method of characteristics. We also present a technique for the transient analysis of lossy coupled lines in inhomogeneous media, which is characterized by multiple propagation modes of unequal phase velocities.
An early estimate for average interconnection length should rely on a few simple parameters. We propose a general power-law relationship to provide an estimate of the number of interconnections crossing a boundary which encloses B blocks or cells rather than the typically utilized Rent relationship. We show that it is necessary to utilize different exponents in the power-law relationships, partitioning coefficients, in order to accurately estimate average interconnection lengths and interconnection densities depending on whether a one-dimensional or two-dimensional placement strategy is used. Based on these findings, an average interconnection length estimate is presented for rectangular arrays which outperforms other existing estimates.
The determination of system size is important for several reasons. It provides a measure of the average interconnection length. It also allows the designer to determine if the logic fits in a desired set of packages. We derive size limitations for the various levels of a packaging hierarchy based on a number of size limiting factors including terminal requirements, cooling, and manufacturing limitations. The techniques are applied to practical examples to assess sizing tradeoffs.
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